SM8750AV View Datasheet(PDF) - Nippon Precision Circuits
Part Name
Description
Manufacturer
SM8750AV Datasheet PDF : 10 Pages
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SM8750AV
Auto-adjust Function
When the serial interface bit CS is set HIGH, the
auto-adjust function starts and operates on the
objects in the sequence described below. In the auto-
adjust sequence cycle, the RDCLK pulsewidth and
DATA delay are set to approximately the center of
the adjustment range.
1. Charge pump circuit and output buffer offset
cancellation
An identical 0.5T signal is added to the
charge/discharge signals and the output on
TVOUT is calibrated to an output voltage of
VREF2.
2. RDCLK pulsewidth
Signals equivalent to the RDCLK HIGH-level
pulsewidth and LOW-level pulsewidth are added
to the internal charge/discharge signals, and the
RDCLK pulsewidths are adjusted to recover a
TVOUT output voltage of VREF2.
3. DATA rising edge delay
The phase difference between the RDCLK rising
edge and DATA rising edge is converted to a
voltage, and the RDCLK rising edge delay is
adjusted to recover a TVOUT output voltage of
VREF2.
Sleep Mode
When the serial interface bit SP is set HIGH, sleep
mode is invoked. In this mode, all circuits other than
the power-ON detection circuit and serial interface
circuit are shutdown to reduce current consumption.
Power-ON Reset
When power is switched ON, a built-in power-ON
reset circuit sets all serial interface bit settings to
LOW (factory preset default), and the auto-adjust
Test Mode
When the serial interface bit TEST1 or TEST0 is set
HIGH, a test mode is invoked. In these modes, the
phase comparator input signals and internal
4. DATA falling edge delay
The phase difference between the RDCLK rising
edge and DATA falling edge is converted to a
voltage, and the RDCLK rising edge delay is
adjusted to recover a TVOUT output voltage of
VREF2.
The CALMON calibration monitor output is high
impedance during the auto-adjust sequence interval.
When auto-adjustment is completed, the CALMON
N-channel open drain turns ON and CALMON goes
LOW, and the CS bit is cleared to LOW.
When the serial interface bit CSDIS is set HIGH, the
auto-adjustment result is disabled, and the external
inputs on RDCLK and DATA are input to the phase
comparator without adjustment. If CS and CSDIS
are both simultaneously set HIGH, the auto-adjust
sequence still takes place but that the result is dis-
abled as soon as the sequence is completed.
When power is switched ON, the auto-adjust
sequence is enabled, and the adjusted values are
approximately in the center of the corresponding
adjustment range.
When operation transfers from sleep mode to normal
operating mode, the auto-adjust settings from the
most recent auto-adjust cycle are restored.
circuit settings are set to the middle of the corre-
sponding adjustment range.
charge/discharge signals are output on CALMON
and TVOUT.
Table 4. Test modes
TEST1
LOW
LOW
HIGH
TEST0
LOW
HIGH
LOW
CALMON
Normal operation
Internal charge signal
Phase comparator RDCLK signal
TVOUT
Normal operation
Internal discharge signal
Phase comparator DATA signal
NIPPON PRECISION CIRCUITS—9
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