NOP, STALL and Deselect Cycles
A67L8316/A67L8318/
A67L7332/A67L7336 Series
1
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
A1
I/O
COMMAND WRITE
D(A1)
2
3
4
5
A2
A3
A4
D(A1)
Q(A2)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
6
7
8
9
10
Q(A3)
STALL
NOP
A5
D(A4)
READ
Q(A5)
tKHQZ
Q(A5)
tKHQX
DESELECT
CONTINUE
DESELECT
: Don't Care
: Undefined
Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a “pause.” A WRITE
is not performed during this cycle.
2. For this waveform, ZZ and OE are tied LOW.
3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The
most recent data may be from the input data register.
PRELIMINARY (March, 1999, Version 0.0)
16
AMIC Technology, Inc.