SLEEP Mode
SLEEP Mode is a low current “Power-down” mode in
which the device is deselected and current is reduced to
ISB2Z. This duration of SLEEP Mode is dictated by the
length of time the ZZ is in a HIGH state. After entering
SLEEP Mode, all inputs except ZZ become disabled and
all outputs go to High-Z.
The ZZ pin is asynchronous, active high input that causes
the device to enter SLEEP Mode. When the ZZ pin
A67L8316/A67L8318/
A67L7332/A67L7336 Series
becomes logic HIGH, ISB2Z is guaranteed after the time
tZZI is met, Any operation pending when entering SLEEP
Mode is not guaranteed to successfully complete.
Therefore, SLEEP Mode (READ or WRITE) must not be
initiated until valid pending operations are completed.
Similarly, when exiting SLEEP Mode during tRZZ, only a
DESELECT or READ cycle should be given while the
SRAM is transitioning out of SLEEP Mode.
SLEEP Mode Electrical Characteristics
(VCC, VCCQ = +3.3V±5%)
Symbol
Parameter
ISB2Z Current during SLEEP Mode
tZZ
ZZ active to input ignored
tRZZ
ZZ inactive to input sampled
tZZI
ZZ active to snooze current
tRZZI
ZZ inactive to exit snooze current
Note : 1. This parameter is sampled.
Conditions
ZZ ≥ VIH
Min.
-
0
0
-
0
Max.
10
2(tKHKH)
2(tKHKH)
2(tKHKH)
Unit
mA
ns
ns
ns
ns
Note
1
1
1
1
SLEEP Mode Waveform
CLK
ZZ
ISUPPLY
ALL INPUTS
(except ZZ)
Output
(Q)
tZZ
tZZI
IISB2Z
tRZZ
tRZZI
DESELECT or READ Only
High-Z
: Don't Care
PRELIMINARY (March, 1999, Version 0.0)
14
AMIC Technology, Inc.