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UC1843A View Datasheet(PDF) - Microsemi Corporation

Part Name
Description
Manufacturer
UC1843A
Microsemi
Microsemi Corporation Microsemi
UC1843A Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
PRODUCTION DATA SHEET
A B S O L U T E M A X I M U M R AT I N G S (Note 1)
Supply Voltage (Low Impedance Source) (VCC) ......................................................... 30V
Supply Voltage (ICC < 30mA) .......................................................................... Self Limiting
Output Current ............................................................................................................. ±1A
Output Energy (Capacitive Load) ................................................................................. 5µJ
Analog Inputs (VFB & ISENSE) ........................................................................ -0.3V to +6.3V
Error Amp Output Sink Current ............................................................................... 10mA
Power Dissipation at TA = 25°C (M Package) .............................................................. 1W
Storage Temperature Range .................................................................... -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) ............................................................. 300°C
Peak Package Solder Reflow Temp. (40 second max. exposure)..........................................260°C (+0, -5)
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect
to Ground. Currents are positive into, negative out of the specified terminal. Pin
numbers refer to DIL packages only.
T H E R MAL DATA
M PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
DM PACKAGE:
95°C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
D PACKAGE:
165°C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
Y PACKAGE:
120°C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
130°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θ numbers are guidelines for the thermal performance of the device/pc-board system.
JA
All of the above assume no ambient airflow
PACKAGE PIN OUTS
COMP 1
VFB 2
ISENSE
3
RT/CT 4
8 VREF
7 VCC
6 OUTPUT
5 GND
M & Y PACKAGE
(Top View)
COMP
VFB
ISENSE
RT/CT
1
8
VREF
2
7
VCC
3
6
OUTPUT
4
5
GND
DM PACKAGE
(Top View)
COMP
N.C.
VFB
N.C.
ISENSE
N.C.
RT/CT
1
14
VREF
2
13
N.C.
3
12
VCC
4
11
VC
5
10
OUTPUT
6
9
GND
7
8
PWR GND
D PACKAGE
(Top View)
RoHS / Pb-free 100% Matte Tin Lead Finish
2
Copyright © 1995
Rev. 1.2a 10/25
 

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