U6815BM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
U6815BM Datasheet PDF : 14 Pages
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11. Noise and Surge Immunity
Parameters
Conducted interferences
Interference suppression
ESD (human body model)
ESD (machine model)
Note: 1. Test pulse 5: VSmax = 40V
Test Conditions
ISO 7637-1
VDE 0879 Part 2
MIL-STD-883D Method 3015.7
EOS/ESD - S 5.2
Value
level 4 (1)
level 5
2 kV
150V
12. Electrical Characteristics
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max. Unit
Current Consumption
Quiescent current (VS)
VVS < 16V, INH or bit SI = low
Pins 5, 10
IVS
40
µA
Quiescent current (VCC)
4.5V < VVCC < 5.5V,
INH or bit SI = low, pin 19
IVCC
20
µA
Supply current (VS)
normal operating
Supply current (VCC)
VVS < 16V, pins 5, 10
all output stages off
IVS
All output stages on, no load
IVS
4.5V < VVCC < 5.5V,
normal operating, pin 19
IVCC
0.8
1.2
mA
10
mA
150
µA
Internal Oscillator Frequency
Frequency
(time-base for delay timers)
fOSC
19
45
kHz
Over- and Undervoltage Detection, Power-on Reset
Power-on reset threshold
Pin 19
Power-on reset delay time
Undervoltage detection threshold
After switching on VVCC
Pins 5, 10
Undervoltage detection hysteresis Pins 5, 10
Undervoltage detection delay
Overvoltage detection threshold
Pins 5, 10
Overvoltage detection hysteresis
Pins 5, 10
Overvoltage detection delay
Input register, Bit 14 (SCT) = high
Overvoltage detection delay
Input register, Bit 14 (SCT) = low
Thermal Prewarning and Shutdown
VVCC
tdPor
VUV
ΔVUV
tdUV
VOV
ΔVOV
tdOV
tdOV
3.4
3.9
4.4
V
30
95
160
µs
5.5
7.0
V
0.4
V
7
21
ms
18
22.5
V
1
V
7
21
ms
1.75
5.25
ms
Thermal prewarning, set
Thermal prewarning, reset
Thermal prewarning hysteresis
Thermal shutdown, off
Thermal shutdown, on
Thermal shutdown hysteresis
Notes: 1. Only valid for version U6815BM-N.
TjPWset
TjPWreset
ΔTjPW
Tj switch off
Tj switch on
ΔTj switch off
125
105
150
130
145
165
°C
125
145
°C
20
K
170
190
°C
150
170
°C
20
K
2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level.
8 U6815BM
4545D–BCD–04/09
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