U630H16PK35G1 View Datasheet(PDF) - Simtek Corporation
Part Name
Description
Manufacturer
U630H16PK35G1 Datasheet PDF : 17 Pages
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U630H16P
Software Mode Selection
E
W
A10 - A0
(hex)
L
H
000
555
2AA
7FF
0F0
70F
L
H
000
555
2AA
7FF
0F0
70E
Mode
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
I/O
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Active
ICC2
Active
Notes
s, t
s, t
s, t
s, t
s, t
s
s, t
s, t
s, t
s, t
s, t
s
s: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA,
7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C.
t: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
Symbol
No. Software Controlled STORE/RECALL
Cycles, u
Alt.
IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactivev
27 STORE Cycle Timew
28 RECALL Cycle Timel
29 Address Setup to Chip Enablex
30 Chip Enable Pulse Widthx, y
31 Chip Disable to Address Changex
tAVAV
tcR
25
35
45
ns
tELQZ tdis(E)SR
600
600
600 ns
tELQXS td(E)S
10
10
10 ms
tELQXR td(E)R
20
20
20 μs
tAVELN tsu(A)SR 0
0
0
ns
tELEHN tw(E)SR 20
25
35
ns
tEHAXN th(A)SR
0
0
0
ns
u: The software sequence is clocked with E controlled READs.
v: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
w: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
x: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
y: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
March 31, 2006
STK Control #ML0037
11
Rev 1.0
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