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TYN808 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
TYN808
ST-Microelectronics
STMicroelectronics ST-Microelectronics
TYN808 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
TN8, TS8 and TYNx08 Series
Fig. 3-2: Relative variation of thermal impedance
junction to ambient versus pulse duration
(recommended pad layout, FR4 PC board for
DPAK).
Fig. 4-1: Relative variation of gate trigger current
and holding current versus junction temperature
for TS8 series.
K = [Zth(j-a)/Rth(j-a)]
1.00
0.10
DPAK
TO-220AB
0.01
1E-2
1E-1
tp(s)
1E+0
1E+1
1E+2 5E+2
Fig. 4-2: Relative variation of gate trigger current
and holding current versus junction temperature
for TN8 & TYN series.
IGT,IH,IL [Tj] / IGT ,IH,IL [Tj = 25 °C]
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40
IGT
-20 0
IH & IL
Rgk = 1k
Tj(°C)
20 40 60 80 100 120 140
Fig. 5: Relative variation of holding current
versus gate-cathode resistance (typical values)
for TS8 series.
IGT,IH,IL [Tj] / IGT ,IH,IL [Tj = 25 °C]
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40
IGT
-20 0
Tj(°C)
20 40 60 80
IH & IL
100 120 140
IH[Rgk] / IH[Rgk = 1k]
Rgk(k)
Fig. 6: Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
for TS8 series.
dV/dt[Rgk] / dV/dt [Rgk = 220]
Rgk(k)
Fig. 7: Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical values)
for TS8 series.
dV/dt[Cgk] / dV/dt [Rgk = 220 ]
15.0
VD = 0.67 x VDRM
Tj = 125°C
12.5
Rgk = 220
10.0
7.5
5.0
2.5
0.0
0
Cgk(nF)
20 40 60 80 100 120 140 160 180 200 220
5/9
 

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