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DAC8408FT View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
DAC8408FT Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DAC8408
WAFER TEST LIMITS at VDD = +5 V; VREF = ؎10 V; VOUTA, B, C, D = 0 V; TA = +25؇C, unless otherwise noted. Specifications apply for
DAC A, B, C, & D.
Parameter
Symbol
Conditions
DAC8408G
Limits
Units
STATIC ACCURACY
Resolution
Nonlinearity1
Differential Nonlinearity
Gain Error
Power Supply Rejection
(VDD = ± 10%)2
IOUT 1A, B, C, D Leakage Current
N
INL
DNL
GFSE
PSR
ILKG
VREF = +10 V
Using Internal RFB
Using Internal RFB
All Digital Inputs = 0 V
REFERENCE INPUT
Reference Input
RIN
Resistance3
Input Resistance Match
RIN
DIGITAL INPUTS
Digital Input Low
VIL
Digital Input High
VIH
Input Current4
IIN
DATA BUS OUTPUTS
Digital Output Low
VOL
Digital Output High
VOH
Output Leakage Current
ILKG
1.6 mA Sink
400 µA Source
POWER SUPPLY
Supply Current5
IDD
Supply Current6
IDD
NOTES
1This is an endpoint linearity specification.
2FSR is Full Scale Range = VREF –1 LSB.
3Input Resistance Temperature Coefficient approximately equals +300 ppm/ °C.
4Logic inputs are MOS gates.Typical input current at +25°C is less than 10 nA.
5All Digital Inputs are either “0” or VDD.
6All Digital Inputs are either VIH or VIL.
8
± 1/2
±1
±1
0.001
± 30
6/14
±1
0.8
2.4
± 1.0
0.4
4
± 1.0
50
1.0
Bits min
LSB max
LSB max
LSB max
%FSR/% max
nA max
kmin/max
% max
V max
V min
µA max
V max
V min
µA max
µA max
mA max
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. A
–5–
 

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