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TPS60110 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
TPS60110 REGULATED 5-V 300-mA LOW-NOISE CHARGE PUMP DC/DC CONVERTER TI
Texas Instruments TI
TPS60110 Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TPS60110
REGULATED 5ĆV 300ĆmA LOWĆNOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215C − JUNE 1999 − REVISED AUGUST 2008
PWP PACKAGE
(TOP VIEW)
GND
1
SYNC
2
ENABLE
3
FB
4
OUT
5
C1+
6
IN
7
C1−
8
PGND
9
PGND
10
20
GND
19
CLK
18
COM
17
SKIP
16
OUT
15
C2+
14
IN
13
C2−
12
PGND
11
PGND
Thermal
Pad
Figure 2. Bottom View of PWP Package,
Showing the Thermal Pad
AVAILABLE OPTIONS
PACKAGE
TSSOP†
(PWP)
TPS60110PWP
This package is available taped and reeled. To order this packaging
option, add an R suffix to the part number (e.g., TPS60110PWPR).
Terminal Functions
TERMINAL
NAME
NO.
CLK
19
C1+
6
C1−
8
C2+
15
C2−
13
COM
18
ENABLE
3
FB
GND
IN
OUT
PGND
SKIP
4
1, 20
7, 14
5, 16
9−12
17
SYNC
2
PowerPAD
I/O
DESCRIPTION
I Input for external clock signal. If the internal clock is used, connect this terminal to GND.
Positive terminal of the charge-pump capacitor C1F
Negative terminal of the charge-pump capacitor C1F
Positive terminal of the charge-pump capacitor C2F
Negative terminal of the charge-pump capacitor C2F
I Mode selection.
When COM is logic low the charge pump operates in push-pull mode to minimize output ripple. When COM is
connected to IN the regulator operates in single-ended mode requiring only one flying capacitor.
I ENABLE Input. The device turns off, the output disconnects from the input, and the supply current decreases
to 0.05 µA when ENABLE is a logic low. ENABLE High may only be applied when VIN is inside the recommended
operating range.
I FEEDBACK input. Connect FB to OUT as close to the load as possible to achieve best regulation. Resistive
divider is on-chip to match internal reference voltage of 1.22 V.
GROUND. Analog ground for internal reference and control circuitry. Connect to PGND through a short trace.
I Supply Input. Connect to an input supply in the 2.7-V to 5.4-V range. Bypass IN to GND with a (CO/2) µF
capacitor. Connect both INs through a short trace.
O Regulated 5-V power output. Connect both OUTs through a short trace and bypass OUT to GND with the output
filter capacitor CO.
PGND power ground. Charge-pump current flows through this pin. Connect all PGNDs together.
I Mode selection. When SKIP is logic low, the charge pump operates in constant-frequency mode. Output ripple
and noise are minimized in this mode. When SKIP is connect to IN, the device operates in pulse skip mode.
Quiescent current is lowest in this mode.
I Selection for external clock signal. Connect to GND to use the internally generated clock signal. Connect to IN
for external synchronization. In this case, the clock signal needs to be fed through CLK.
Must be soldered to achieve appropriate power dissipation. Should be connected to PGND.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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