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T0P246Y Просмотр технического описания (PDF) - Power Integrations, Inc

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T0P246Y Datasheet PDF : 52 Pages
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internal capacitance between two voltage levels to create
a sawtooth waveform for the pulse width modulator. This
oscillator sets the pulse width modulator/current limit latch at
the beginning of each cycle.
The nominal switching frequency of 132 kHz was chosen to
minimize transformer size while keeping the fundamental EMI
frequency below 150 kHz. The FREQUENCY pin (available
only in Y, R or F package), when shorted to the CONTROL pin,
lowers the switching frequency to 66 kHz (half frequency) which
may be preferable in some cases such as noise sensitive video
applications or a high efficiency standby mode. Otherwise, the
FREQUENCY pin should be connected to the SOURCE pin
for the default 132 kHz.
To further reduce the EMI level, the switching frequency is
jittered (frequency modulated) by approximately ±4 kHz at
250 Hz (typical) rate as shown in Figure 9. Figure 46 shows
the typical improvement of EMI measurements with frequency
Pulse Width Modulator and Maximum Duty Cycle
The pulse width modulator implements voltage mode control
by driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin that
is in excess of the internal supply current of the chip (see
Figure 7). The excess current is the feedback error signal that
appears across RE (see Figure 2). This signal is filtered by an RC
network with a typical corner frequency of 7 kHz to reduce the
effect of switching noise in the chip supply current generated
by the MOSFET gate driver. The filtered error signal is
compared with the internal oscillator sawtooth waveform to
generate the duty cycle waveform. As the control current
increases, the duty cycle decreases. A clock signal from the
oscillator sets a latch which turns on the output MOSFET. The
pulse width modulator resets the latch, turning off the output
MOSFET. Note that a minimum current must be driven into
the CONTROL pin before the duty cycle begins to change.
The maximum duty cycle, DCMAX, is set at a default maximum
value of 78% (typical). However, by connecting the LINE-
SENSE or MULTI-FUNCTION pin (depending on the
package) to the rectified DC high voltage bus through a
resistor with appropriate value, the maximum duty cycle can
be made to decrease from 78% to 38% (typical) as shown in
Figure 11 when input line voltage increases (see line feed
forward with DCMAX reduction).
Light Load Frequency Reduction
The pulse width modulator duty cycle reduces as the load at
the power supply output decreases. This reduction in duty
cycle is proportional to the current flowing into the CONTROL
pin. As the CONTROL pin current increases, the duty cycle
decreases linearly towards a duty cycle of 10%. Below 10%
duty cycle, to maintain high efficiency at light loads, the
136 kHz
128 kHz
4 ms
Figure 9. Switching Frequency Jitter (Idealized VDRAIN Waveforms).
frequency is also reduced linearly until a minimum frequency
is reached at a duty cycle of 0% (refer to Figure 7). The
minimum frequency is typically 30 kHz and 15 kHz for
132 kHz and 66 kHz operation, respectively.
This feature allows a power supply to operate at lower
frequency at light loads thus lowering the switching losses
while maintaining good cross regulation performance and low
output ripple.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifier in primary side feedback applications. The shunt
regulator voltage is accurately derived from a temperature-
compensated bandgap reference. The gain of the error
amplifier is set by the CONTROL pin dynamic impedance.
The CONTROL pin clamps external circuit signals to the VC
voltage level. The CONTROL pin current in excess of the
supply current is separated by the shunt regulator and flows
through RE as a voltage error signal.
On-Chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET on-state drain
to source voltage, VDS(ON) with a threshold voltage. High drain
current causes VDS(ON) to exceed the threshold voltage and turns
the output MOSFET off until the start of the next clock cycle.
The current limit comparator threshold voltage is temperature
compensated to minimize the variation of the current limit due
to temperature related changes in RDS(ON)of the output MOSFET.
The default current limit of TOPSwitch-GX is preset internally.
However, with a resistor connected between EXTERNAL
CURRENT LIMIT (X) pin (Y, R or F package) or MULTI-
FUNCTION (M) pin (P or G package) and SOURCE pin,
current limit can be programmed externally to a lower level
between 30% and 100% of the default current limit. Please
refer to the graphs in the typical performance characteristics
section for the selection of the resistor value. By setting current
limit low, a larger TOPSwitch-GX than necessary for the power
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