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TSC80C31-36MYD View Datasheet(PDF) - Temic Semiconductors

Part NameDescriptionManufacturer
TSC80C31-36MYD CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller Temic
Temic Semiconductors Temic
TSC80C31-36MYD Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
TSC80C31/80C51
Explanation of the AC Symbol
Each timing symbol has 5 characters. The first character
is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
Example :
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A : Address.
C : Clock.
D : Input data.
H : Logic level HIGH
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P : PSEN.
Q : Output data.
R : READ signal.
T : Time.
V : Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z : Float.
AC Parameters
TA= 0 to + 70°C ; Vss= 0 V ; Vcc= 5 V ± 10 % ; F= 0 to 44 MHz
TA= 0 to +70°C ; Vss= 0 V ; 2.7 V <Vcc < 5.5 V ; F= 0 to 16 MHz
TA=–40° to +85°C; Vss= 0 V; 2.7 V<Vcc <5.5 V ; F= 0 to 16 MHz
TA= –55° + 125°C; Vss= 0 V; Vcc= 5 V ± 10 % ; F= 0 to 40 MHz
(Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load
Capacitance for all other outputs = 80 pF)
External Program Memory Characteristics (values in ns)
SYMBOL
PARAMETER
TLHLL ALE Pulse Width
TAVLL Address valid to ALE
TLLAX Address Hold After ALE
TLLIV ALE to valid instr in
TLLPL ALE to PSEN
TPLPH PSEN pulse Width
TPLIV PSEN to valid instr in
TPXIX Input instr Hold After PSEN
TPXIZ Input instr Float After PSEN
TPXAV PSEN to Address Valid
TAVIV Address to Valid instr in
TPLAZ PSEN low to Address Float
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 44 MHz
min max min max min max min max min max min max min max
110
90
70
60
50
40
30
40
30
20
15
10
9
7
35
35
35
35
35
30
20
185
170
130
100
80
70
65
45
40
30
25
20
15
12
165
130
100
80
75
65
54
125
110
85
65
50
45
35
0
0
0
0
0
0
0
50
45
35
30
25
20
10
55
50
40
35
30
25
15
230
210
170
130
90
80
70
10
10
8
6
5
5
5
External Program Memory Read Cycle
TAVIV
14
MATRA MHS
Rev. E (14 Jan.97)
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