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TSC80C31-40AGDP883 View Datasheet(PDF) - Temic Semiconductors

Part NameTSC80C31-40AGDP883 Temic
Temic Semiconductors Temic
DescriptionCMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller


TSC80C31-40AGDP883 Datasheet PDF : 19 Pages
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TSC80C31/80C51
Absolute Maximum Ratings*
Ambient Temperature Under Bias :
A = Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W**
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
* Notice
Stresses above those listed under “ Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Parameters
TA = –40°C + 125°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 40 MHz
Symbol
Parameter
VIL Input Low Voltage
VIH Input High Voltage (Except XTAL and RST)
VIH1 Input High Voltage (for XTAL and RST)
VOL Output Low Voltage (Port 1, 2 and 3) (4)
VOL1 Output Low Voltage (Port 0, ALE, PSEN) (4)
VOH Output High Voltage Port 1, 2 and 3
VOH1 Output High Voltage (Port 0, ALE, PSEN)
IIL
ILI
ITL
IPD
RRST
CIO
ICC
Logical 0 Input Current (Ports 1, 2 and 3)
Input leakage Current
Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
Power Down Current
RST Pulldown Resistor
Capacitance of I/O Buffer
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq 12 MHz Icc op max = 0.9 Freq (MHz) + 5
Icc idle max = 0.3 Freq (MHz) + 1.7
Freq 20 MHz Icc op typ = 0.7 Freq (MHz)
Freq 20 MHz Icc op typ = 0.5 Freq (MHz) + 4
Freq 20 MHz Icc idle typ = 0.16 Freq (MHz) + 0.4
Freq 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2
Min
Typ (3) Max Unit Test Conditions
– 0.5
0.2 Vcc – 0.1 V
0.2 Vcc + 0.9
Vcc + 0.5 V
0.7 Vcc
Vcc + 0.5 V
0.3
V IOL = 100 µA
0.45
V IOL = 1.6 mA (2)
1.0
V IOL = 3.5 mA
0.3
V IOL = 200 µA
0.45
V IOL = 3.2 mA (2)
1.0
V IOL = 7.0 mA
Vcc – 0.3
V IOH = – 10 µA
Vcc – 0.7
V IOH = – 30 µA
Vcc – 1.5
V IOH = – 60 µA
VCC = 5 V ± 10 %
Vcc – 0.3
V IOH = – 200 µA
Vcc – 0.7
V IOH = – 3.2 mA
Vcc – 1.5
V IOH = – 7.0 mA
VCC = 5 V ± 10 %
– 75
µA Vin = 0.45 V
±10
µA 0.45 < Vin < Vcc
– 750
µA Vin = 2.0 V
5
75
µA Vcc = 2.0 V to 5.5 V (1)
50
90
200
KW
10
pF fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
0.7
1.8
mA
0.5
1
mA
4.2
9
mA
1.4
3.5
mA
mA
mA
mA
mA
mA
mA
10
MATRA MHS
Rev. E (14 Jan.97)
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Description
The TSC80C31/80C51 is high performance SCMOS versions of the 8051 NMOS single chip 8 bit µC. The fully static design of the TSC80C31/80C51 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.
The TSC80C31/80C51 retains all the features of the 8051 : 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ; two 16 bit timers ; a 5-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits.

Features
Power control modes
128 bytes of RAM
4 K bytes of ROM (TSC80C31/80C51)
32 programmable I/O lines
Two 16 bit timer/counter
64 K program memory space
64 K data memory space

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