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M48T18-150MH1F View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48T18-150MH1F
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48T18-150MH1F Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M48T08, M48T08Y, M48T18
WRITE Mode
The M48T08/18/08Y is in the WRITE Mode when-
ever W, E1, and E2 are active. The start of a
WRITE is referenced from the latter occurring fall-
ing edge of W or E1, or the rising edge of E2. A
WRITE is terminated by the earlier rising edge of
W or E1, or the falling edge of E2. The addresses
must be held valid throughout the cycle. E1 or W
must return high or E2 low for a minimum of tE1HAX
or tE2LAX from Chip Enable or tWHAX from WRITE
Enable prior to the initiation of another READ or
WRITE Cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX af-
terward. G should be kept high during WRITE Cy-
cles to avoid bus contention; however, if the output
bus has been activated by a low on E1 and G and
a high on E2, a low on W will disable the outputs
tWLQZ after W falls.
Figure 8. WRITE Enable Controlled, WRITE AC Waveform
A0-A12
E1
E2
tAVE1L
tAVE2H
tAVWL
tAVAV
VALID
tAVWH
tWLWH
tWHAX
W
DQ0-DQ7
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI00963
9/27
 

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