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M48T08-150MH1F View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48T08-150MH1F
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48T08-150MH1F Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M48T08, M48T08Y, M48T18
READ Mode
The M48T08/18/08Y is in the READ Mode when-
ever W (WRITE Enable) is high, E1 (Chip Enable
1) is low, and E2 (Chip Enable 2) is high. The de-
vice architecture allows ripple-through access of
data from eight of 65,536 locations in the static
storage array. Thus, the unique address specified
by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within address
access time (tAVQV) after the last address input
signal is stable, providing that the E1, E2, and G
access times are also satisfied. If the E1, E2 and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
times (tE1LQV or tE2HQV) or Output Enable Access
time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are ac-
tivated before tAVQV, the data lines will be driven to
an indeterminate state until tAVQV. If the address
inputs are changed while E1, E2 and G remain ac-
tive, output data will remain valid for Output Data
Hold time (tAXQX) but will go indeterminate until the
next address access.
Figure 7. READ Mode AC Waveforms
A0-A12
E1
E2
G
DQ0-DQ7
tAVQV
tE1LQV
tAVAV
VALID
tE1LQX
tE2HQV
tE2HQX
tGLQV
tGLQX
tAXQX
tE1HQZ
tE2LQZ
tGHQZ
VALID
Note: WRITE Enable (W) = High.
AI00962
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