E28F004S5-100 View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
E28F004S5-100 Datasheet PDF : 37 Pages
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E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
1FFFFF
Block 31
Reserved for
Future Implementation
1F0002
1F0000
Block 31 Lock Configuration
Reserved for
Future Implementation
(Blocks 16 through 30)
0FFFFF
Block 15
Reserved for
Future Implementation
0F0002
0F0000
Block 15 Lock Configuration
Reserved for
Future Implementation
07FFFF
(Blocks 8 through 14)
Block 7
Reserved for
Future Implementation
16-Mbit
070002
070000
01FFFF
Block 7 Lock Configuration
Reserved for
Future Implementation
(Blocks 2 through 14)
8-Mbit
Block 1
Reserved for
Future Implementation
4-Mbit
010002
010000
00FFFF
000003
000002
000001
000000
Block 1 Lock Configuration
Reserved for
Future Implementation
Block 0
Reserved For
Future Implementation
Master Lock Configuration
Block 0 Lock Configuration
Device Code
Manufacturer Code
3.5 Read Identifier Codes
Operation
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and master lock
configuration code (see Figure 5). Using the
manufacturer and device codes, the system
software can automatically match the device with its
proper algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
3.6 Write
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active
and OE# = VIH. The address and data needed to
execute a command are latched on the rising edge
of WE# or CE# (whichever goes high first).
Standard microprocessor write timings are used.
Figure 17 illustrates a write operation.
4.0 COMMAND DEFINITIONS
When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing VPPH1/2 on VPP enables
successful block erase, program, and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Figure 5. Device Identifier Code Memory Map
PRODUCT PREVIEW
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