DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

E-TDA7590 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
E-TDA7590 Datasheet PDF : 40 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin description
TDA7590
Table 1.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Pin function (continued)
Name
Type
Description
HAD[7]
HAD[6]
I/O
Host 8-bit data line 7. Host Data Bus and/or address lines when in
multiplexed mode.
I/O
Host 8-bit data line 6. Host Data Bus and/or address lines when in
multiplexed mode.
HAD[5]
I/O
Host 8-bit data line 5. Host Data Bus and/or address lines when in
multiplexed mode.
HAD[4]
I/O
Host 8-bit data line 4. Host Data Bus and/or address lines when in
multiplexed mode.
COREVDD
I Core Power Supply.
COREVSS
I Core Ground.
HAD[3]
I/O
Host 8-bit data line 3. Host Data Bus and/or address lines when in
multiplexed mode.
HAD[2]
I/O
Host 8-bit data line 2. Host Data Bus and/or address lines when in
multiplexed mode.
HAD[1]
HAD[0]
I/O
Host 8-bit data line 1. Host Data Bus and/or address lines when in
multiplexed mode.
I/O
Host 8-bit data line 0. Host Data Bus and/or address lines when in
multiplexed mode.
AA[3]
O
Address Attributes line 3.Port A address attributes/chip select pins with
programmable polarity.
AA[2]
O
Address Attributes line 2.Port A address attributes/chip select pins with
programmable polarity.
BR_N
O
Bus Request. Asserted when Port A requires bus mastership to perform off-
chip accesses.
BB_N
IOVDD
I/O
Bus Busy. Asserted by Port A when bus_busy_in_n is negated and BG_N is
asserted.
I IO Power Supply.
IOVSS
I IO Ground.
WEN_N
O Write Enable.
OEN_N
O Output Enable.
AA[1]
O
Address Attributes line 1.Port A address attributes/chip select pins with
programmable polarity.
AA[0]
O
Address Attributes line 0.Port A address attributes/chip select pins with
programmable polarity.
BG_N
Bus Grant. When asserted, Port A becomes the bus master elect. Bus
I mastership
is attained when bus busy is negated by the current bus master.
AB[0]
O Address Bus line 0. Port A external address bus.
AB[1]
O Address Bus line 1. Port A external address bus.
IOVDD
I IO Power Supply.
8/40
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]