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E-TDA7566 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
E-TDA7566 4 x 40 W multifunction quad power amplifier with built-in diagnostics features ST-Microelectronics
STMicroelectronics ST-Microelectronics
E-TDA7566 Datasheet PDF : 29 Pages
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TDA7566
5
I2C bus interface
I2C bus interface
Data transmission from microprocessor to the TDA7566 and vice versa takes place through
the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to
positive supply voltage must be connected).
5.1
Data validity
As shown by Figure 25, the data on the SDA line must be stable during the high period of
the clock.
The HIGH and LOW state of the data line can only change when the clock signal on the SCL
line is LOW.
5.2
Start and stop conditions
As shown by Figure 26 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
5.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
5.4
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 27). The receiver** the acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock
pulse.
* Transmitter
– master (µP) when it writes an address to the TDA7566
– slave (TDA7566) when the µP reads a data byte from TDA7566
** Receiver
– slave (TDA7566) when the µP writes an address to the TDA7566
– master (µP) when it reads a data byte from TDA7566
Figure 25. Data validity on the I2C bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Doc ID 9801Rev 5
19/29
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