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80023 Ver la hoja de datos (PDF) - Philips Electronics

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80023 IC card interface Philips
Philips Electronics Philips
80023 Datasheet PDF : 28 Pages
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Philips Semiconductors
IC card interface
Product specification
TDA8002
Table 1 Clock circuitry definition
MODE
CLKSEL
HIGH
HIGH
HIGH
HIGH
HIGH
LOW(2)
LOW
LOW
LOW
LOW
HIGH
X(1)
Notes
1. X = don’t care.
2. In low-power mode.
3. fint = 32 kHz in low-power mode.
CLKDIV1
HIGH
LOW
LOW
HIGH
X(1)
X(1)
CLKDIV2
LOW
LOW
HIGH
HIGH
X(1)
X(1)
FREQUENCY
OF CLK
12fint
14fxtal
12fxtal
STOP LOW
STROBE
STOP LOW
FREQUENCY
OF CLKOUT
12fint
fxtal
fxtal
fxtal
fxtal
12fint(3)
I/O circuitry
The three I/O transceivers are identical. The state is HIGH
for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and
AUX2UC). Pin I/O is referenced to VCC and pin I/OUC to
VDD, thus ensuring proper operation in case VCC VDD.
The first side on which a falling edge is detected becomes
a master (input). An anti-latch circuitry first disables the
detection of the falling edge on the other side, which
becomes slave (output).
After a delay time td (about 50 ns), the logic 0 present on
the master side is transferred on the slave side.
When the input is back to HIGH level, a current booster is
turned on during the delay td on the output side and then
both sides are back to their idle state, ready to detect the
next logic 0 on any side.
In case of a conflict, both lines may remain LOW until the
software enables the lines to be HIGH. The anti-latch
circuitry ensures that the lines do not remain LOW if both
sides return HIGH, regardless of the prior conditions.
The maximum frequency on the lines is approximately
1 MHz.
handbook, full pagewidthI/O
I/OUC
td
1997 Nov 04
td
td
conflict
idle
MGD703
Fig.6 Master and slave signals.
8
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