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80023 查看數據表(PDF) - Philips Electronics

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80023 IC card interface Philips
Philips Electronics Philips
80023 Datasheet PDF : 28 Pages
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Philips Semiconductors
IC card interface
Product specification
Power supply
The supply pins for the chip are VDDA, VDDD, AGND,
DGND1 and DGND2. VDDA and VDDD (i.e. VDD) should be
in the range of 3.0 to 6.5 V. All card contacts remain
inactive during power-up or power-down.
On power-up, the logic is reset by an internal signal.
The sequencer is not activated until VDD reaches
Vth2 + Vhys2 (see Fig.5). When VDD falls below Vth2, an
automatic deactivation sequence of the contacts is
Supply voltage supervisor (VDD)
This block surveys the VDD supply. A defined reset pulse
of 10 ms minimum (tW) can be retriggered and is delivered
on the ALARM outputs during power-up or power-down of
VDD (see Fig.5). This signal is also used for eliminating the
spikes on card contacts during power-up or power-down.
When VDD reaches Vth2 + Vhys2, an internal delay is
started. The ALARM outputs are active until this delay has
expired. When VDD falls below Vth2, ALARM is activated
and a deactivation sequence of the contacts is performed.
For 3 V supply, the supervisor option must be chosen at
3 V. For 5 V supply, both options (3 or 5 V) may be chosen
depending on the application.
Clock circuitry
The TDA8002 supports both synchronous and
asynchronous cards (I2C-bus memories requiring an
acknowledge signal from the master are not supported).
There are three methods to clock the circuitry:
Apply a clock signal to pin STROBE
Use of an internal RC oscillator
Use of a quartz oscillator which should be connected
between pins XTAL1 and XTAL2.
When CLKSEL is HIGH, the clock should be applied on the
STROBE pin, and when CLKSEL is LOW, one of the
internal oscillators is used.
When an internal clock is used, the clock output is
available on pin CLKOUT. The RC oscillator is selected by
making CLKDIV1 HIGH and CLKDIV2 LOW. The clock
output to the card is available on pin CLK. The frequency
of the card clock can be the input frequency divided by
2 or 4, STOP LOW or 1.25 MHz, depending on the states
of CLKDIV1 or CLKDIV2 (see Table 1).
Do not change CLKSEL during activation. When in
low-power (sleep) mode, the internal oscillator frequency
which is available on pin CLKOUT is lowered to
approximately 16 kHz for power-economy purposes.
handbook, full pagewidth
Vth2 + Vhys2
1997 Nov 04
Fig.5 Alarm as a function of VDD (pulse width 10 ms).
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