7025ERPQS35 View Datasheet(PDF) - MAXWELL TECHNOLOGIES

Part Name

Description

Manufacturer

7025ERPQS35

(8K x 16-Bit) Dual Port RAM High-Speed CMOS

MAXWELL TECHNOLOGIES 

(8K x 16-Bit) Dual Port RAM High-Speed CMOS

7025E

FIGURE 7. TIMING WAVEFORM OF WRITE CYCLE NO. 2, CS CONTROLLED TIMING 1,2,3,5

FIGURE 8. TIMING WAVEFORM OF WRITE WITH BUSY (FOR SLAVE)

1. R/W must be high during all address transitions.

2. A write occurs during the overlap (tSW to tWF) of a low CS or SEM and a low R/W.

3. T.WF is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the

high impedance state.

6. Transitions measured = 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sam-

ple and not 100% tested.

7. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of two or (tWZ +tDW) to allow

the I/O driver to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled

write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

8. To access RAM, CS = VIL, SEM = VIH.

9. To access upper byte, CS = VIL, UB = VIL, SEM = VIH.

To access lower byte, CS = VIL, LB = VIL, SEM = VIH.

1000586

12.19.01 Rev 2

All data sheets are subject to change without notice 13

©2001 Maxwell Technologies

All rights reserved.

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