Philips Semiconductors
Quadruple filter DAC
Product specification
TDA1314T
SYMBOL
PARAMETER
CONDITIONS
DIGITAL
I2S-BUS, UP-SAMPLING FILTER AND NOISE SHAPER
fSCK
serial clock input
ASF = 38 kHz
frequency
tLC
serial clock LOW time
at 20% VDDD; T = f--S---1-C---K--
tHC
serial clock HIGH time
at 70% VDDD; T = f--S---1-C---K--
fWS
word select input
frequency
tsr
set-up time from SDF,
SDR and WS to HIGH
T = -f-S---1-C---K--
going edge of SCK
thr
hold time from SDF, SDR
and WS to HIGH going
T = -f-S---1-C---K--
edge of SCK
fMCLK
master clock input
frequency
N × 4 × fWS;
where N = integer
tMLC
master clock LOW time
TM = -f-S---1-C---K--
tMHC
master clock HIGH time TM = -f-S---1-C---K--
PR
pass band ripple of
with sample-and-hold
digital filter
from DAC
αSB
stop band attenuation fi > 22 kHz; no post filter
MIN.
TYP.
MAX.
UNIT
1.368
−
0.35T
−
0.35T
−
38
44.1
0.2T
−
19.456
−
−
48
−
MHz
µs
µs
kHz
µs
0
−
−
µs
45 × 4fWS 64 × 4fWS 128 × 4fWS kHz
0.35TM −
−
µs
0.35TM −
−
µs
−
0.46
−
dB
29
−
−
dB
August 1994
11