Philips Semiconductors
Stereo continuous calibration
DAC (CC-DAC)
Preliminary specification
TDA1312A; TDA1312AT
CHARACTERISTICS
VDD = 5 V; Tamb = 25 °C; measured in Fig.1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
Supply
VDD
positive supply voltage
IDD
supply current
4.0
at code 0000H
−
Digital inputs; pins WS, BCK and DATA
IIL
input leakage current LOW
VI = 0 V
−
IIH
input leakage current HIGH
VI = 5 V
−
fBCK
clock frequency
−
BR
bit rate data input
−
fWS
word select input frequency
−
Timing (see Fig.4)
tr
rise time
−
tf
fall time
−
tCY
bit clock cycle time
54
tBCKH
bit clock pulse width HIGH
15
tBCKL
bit clock pulse width LOW
15
tSU;DAT
data set-up time
12
tHD:DAT
data hold time to bit clock
2
tHD:WS
word select hold time
2
tSU;WS
word select set-up time
12
Analog outputs; pins VOL and VOR
VFS
TCFS
VOFF
(THD+N)/S
full-scale voltage
1.8
full-scale temperature coefficient
−
offset voltage
at code 1000H
0.42
total harmonic distortion plus noise at 0 dB signal level; −
note 1
−
at −60 dB signal level; −
note 1
−
at −60 dB signal level; −
A-weighted; note1
−
at 0 dB signal level; −
f = 20 Hz to 20 kHz −
TYP.
5.0
3.4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
2.0
±400
0.47
−68
0.04
−30
3
−33
2
−65
0.05
MAX.
5.5
6.0
10
10
18.4
18.4
384
12
12
−
−
−
−
−
−
−
2.2
−
0.52
−63
0.07
−24
6
−
−
−61
0.09
UNIT
V
mA
µA
µA
MHz
Mbits/s
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
ppm
V
dB
%
dB
%
dB
%
dB
%
July 1993
7