TC58256AFT View Datasheet(PDF) - Toshiba

Part Name

Description

Manufacturer

TC58256AFT

256-MBIT (32M x 8 BITS) CMOS NAND E2PROM

Toshiba 

TC58256AFT

(12) Several programming cycles on the same page (Partial Page Program)

A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:

1st programming Data Pattern 1

All 1s

2nd programming

All 1s

Data Pattern 2

All 1s

nth programming

All 1s

Data Pattern 3

Result Data Pattern 1 Data Pattern 2

Data Pattern 3

Figure 24.

Note: The input data for unprogrammed or previously programmed page segments must be “1”

(i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”).

(13) Note regarding the RE signal

RE The internal column address counter is incremented synchronously with the RE clock in Read mode.

Therefore, once the device has been set to Read mode by a “00H”, “01H” or “50H” command, the internal

column address counter is incremented by the RE clock independently of the address input timing, If the

RE clock input pulses start before the address input, and the pointer reaches the last column address, an

internal read operation (array to register) will occur and the device will enter Busy state. (Refer to Figure 25.)

I/O

00H/01H/50H

Address input

WE

RE

RY/BY

Figure 25.

Hence the RE clock input must start after the address input.

2001-05-30 30/33

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