|Description||3-Pin Reset Monitor|
|TC1272ALVNBTR Datasheet PDF : 12 Pages |
3.0 APPLICATIONS INFORMATION
3.1 VDD Transient Rejection
The TC1272A provides accurate VDD monitoring and
reset timing during power-up, power-down and brown-
out/sag conditions. These devices also reject negative-
going transients (glitches) on the power supply line.
Figure 3-1 shows the maximum transient duration vs.
maximum negative excursion (overdrive) for glitch
rejection. Any combination of duration and overdrive
that lies under the curve will not generate a reset
TA = +25°C
Reset Comparator Overdrive
[VTH - VDD] (mv)
Reset Comparator Overdrive (mV)
[VTH - VDD] (mv)
Duration vs. Overdrive for Glitch Rejection at
Combinations above the curve are detected as a
brown-out or power-down condition. Transient immu-
nity can be improved by adding a capacitor in close
proximity to the VDD pin of the TC1272A.
3.2 RESET Signal Integrity During
The TC1272A RESET output is valid to VDD = 1.0V.
Below this voltage, the output becomes an "open cir-
cuit" and does not sink current. This means CMOS
logic inputs to the microcontroller will be floating at an
undetermined voltage. Most digital systems are com-
pletely shut down well above this voltage. However, in
situations where RESET must be maintained valid to
VDD = 0V, a pull-down resistor must be connected from
RESET to ground to discharge stray capacitances and
hold the output low (Figure 3-2). This resistor value,
though not critical, should be chosen such that it does
not appreciably load RESET under normal operation
(100 kΩ will be suitable for most applications).
The addition of R1 at the
RESET output of the TC1272A ensures that the
RESET output is valid to VDD = 0V.
2004 Microchip Technology Inc.
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