Table 4-2 shows the various device trip point options
and their VTRIP(MAX) and VTRIP(MIN) voltages. Also the
negative percentage change from common regulated
voltages is shown.
In the case where VDD is falling from the regulated volt-
age, as the VDD crosses the VTRIP voltage the
RST/RST pin is driven active. Now the desired circuitry
is in reset, or the circuitry has the indication that the
VDD is below the selected VTRIP.
In the case where VDD is rising. As the VDD crosses the
VTRIP voltage, the RST/RST pin is driven inactive after
the Reset Delay Timer elapses. Now the desired cir-
cuitry is released from reset and will start to operate in
its normal mode, or the circuitry has the indication that
the VDD is above the selected VTRIP.
TABLE 4-2: SELECTING THE TRIP POINT
- % From
5.0V 3.3V 3.0V
4.50V 10.0% —
4.50V 10.0% —
4.25V 15.0% —
— 4.5% —
— 9.2% —
— 9.2% —
— 13.7% —
Voltage regulator circuit must have tighter
tolerance (%) than VTRIP(MAX) % from
Circuitry being reset must have a wider
tolerance (%) than VTRIP(MIN) % from
The TC1270A/TC1270AN/TC1271A devices are
optimized to reject fast transient glitches on the VDD
line. If the low input signal (which is below VTRIP) is not
rejected, the Reset output is driven active within 50 µs
of VDD falling through the Reset voltage threshold.
After the device exits the Reset condition, the delay
circuitry will hold the RST/RST pin active until the
appropriate Reset delay time (tRST) has elapsed.
During device power up, the input voltage is below the
Trip Point voltage. The device must enter the valid
operating range for the device to start operation.
There is also a minimal hysteresis (VHYS) on the trip
point. This is so that small noise signals on the device
voltage (VDD) do not cause the Reset pin (RST/RST) to
“jitter” (change between driving an active and inactive).
The characterization graphs shown in Figures 2-13
through 2-15 shows the device hysteresis as a percent-
age of the voltage trip point (VTRIP).
The Reset Delay Timer (tRST) gives a time based hys-
teresis for the system.
As the device VDD rises, the device’s Reset circuit will
remain active until the voltage rises above the “actual”
trip point (VTRIP).
Figure 4-7 shows a power-up sequence and the wave-
form of the RST and RST pins. As the device powers
up, the voltage will start below the valid operating volt-
age of the device. At this voltage, the RST/RST output
is not valid. Once the voltage is above the minimum
operating voltage (1V) and below the selected VTRIP,
the Reset output will be active.
Once the device voltage rises above the VTRIP voltage,
the Reset delay timer (tRST) starts. When the Reset
delay timer times out, the Reset output (RST/RST) is
Note 1: Additional system current is consumed
during the tRST time.
2: The TC1270AN requires an external
RST/RST pin Operation
© 2007 Microchip Technology Inc.