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T-8207-BAL-DT Просмотр технического описания (PDF) - Agere -> LSI Corporation

Номер в каталогеКомпоненты Описаниепроизводитель
T-8207-BAL-DT CelXpres™ ATM Interconnect Agere
Agere -> LSI Corporation Agere
T-8207-BAL-DT Datasheet PDF : 158 Pages
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Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
Table of Contents (continued)
Table
Page
Table 100. PPD Memory Write (PPDMW) (0418h) ............................................................................................. 124
Table 101. PHY Port X Transmit Count Structure (PPXTXCNT) (0600h to 067Ch) ............................................ 125
Table 102. PHY Port X Receive Count Structure (PPXRXCNT) (0700h to 07F8h) ............................................. 126
Table 103. LUT X Configuration 1 Structure (LUTXCF1) (0704h to 077Ch)......................................................... 127
Table 104. SDRAM Control (SCT) (0400h) ......................................................................................................... 128
Table 105. SDRAM Interrupt Status (SIS) (0402h) ............................................................................................. 128
Table 106. SDRAM Interrupt Enable (SIE) (0404h) ............................................................................................ 128
Table 107. SDRAM Configuration (SCF) (0408h) ............................................................................................... 129
Table 108. Refresh (RFRSH) (0410h) ................................................................................................................ 130
Table 109. Refresh Lateness (RFRSHL) (0412h) ............................................................................................... 130
Table 110. Idle State 1 (IS1) (0420h) .................................................................................................................. 130
Table 111. Idle State 2 (IS2) (0422h) .................................................................................................................. 130
Table 112. Manual Access State 1 (MAS1) (0424h) ........................................................................................... 131
Table 113. Manual Access State 2 (MAS2) (0426h) ........................................................................................... 131
Table 114. SDRAM Interrupt Service Request 4 (SISR4) (0438h) ........................................................................ 132
Table 115. SDRAM Interrupt Service Request 3 (SISR3) (043Ah)........................................................................ 132
Table 116. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) ..................................................................... 132
Table 117. SDRAM Interrupt Service Request 2 (SISR2) (043Eh) ..................................................................... 132
Table 118. Queue X (QX) (0440h to 04BEh) ....................................................................................................... 133
Table 119. Queue X Definition Structure (QXDEF) (2000h to 27E0h) ................................................................. 135
Table 120. Control Cell Receive Extended Memory (CCRXEM) (0800h to 0832h) ............................................. 137
Table 121. Control Cell Transmit Extended Memory (CCTXEM) (0900h to 0936h) ............................................ 137
Table 122. PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) (0C00h to 0C1Eh)............... 138
Table 123. PHY Port X Multicast Memory (PPXMM) (0C20h to 0DE0h) ............................................................. 139
Table 124. PPD Memory (PPDM) (1000h to 13FEh) .......................................................................................... 140
Table 125. Translation RAM Memory (TRAM) (100000h to 17FFFEh) ............................................................... 141
Table 126. SDRAM (SDRAM) (2000000h to 3FFFFFEh) ................................................................................... 141
Table 127. Maximum Rating Parameters and Values.......................................................................................... 142
Table 128. Recommended Operating Conditions ................................................................................................ 142
Table 129. HBM ESD Threshold .......................................................................................................................... 142
Table 130. Crystal Specifications ........................................................................................................................ 143
Table 131. External Clock Requirements............................................................................................................. 143
Table 132. dc Electrical Characteristics .............................................................................................................. 144
Table 133. Input Clocks ...................................................................................................................................... 145
Table 134. Output Clocks .................................................................................................................................... 145
Table 135. Nonmultiplexed Intel Mode Write Access Timing .............................................................................. 147
Table 136. Nonmultiplexed Intel Mode Read Access Timing .............................................................................. 147
Table 137. Motorola Mode Write Access Timing ................................................................................................. 149
Table 138. Motorola Mode Read Access Timing ................................................................................................. 149
Table 139. Multiplexed Intel Mode Write Access Timing .................................................................................... 151
Table 140. Multiplexed Intel Mode Read Access Timing ..................................................................................... 151
Table 141. TX UTOPIA Timing (70 pF Load on Outputs) ................................................................................... 152
Table 142. RX UTOPIA Timing (70 pF Load on Outputs) ................................................................................... 152
Table 143. External LUT Memory Read Timing (cyc_per_acc = 2) .................................................................... 154
Table 144. External LUT Memory Read Timing (cyc_per_acc = 3) .................................................................... 154
Table 145. External LUT Memory Write Timing (cyc_per_acc = 2) .................................................................... 154
Table 146. External LUT Memory Write Timing (cyc_per_acc = 3) .................................................................... 154
Table 147. Cell Bus Timing ................................................................................................................................. 155
Table 148. SDRAM Interface Timing .................................................................................................................. 156
Agere Systems Inc.
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