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T-8207-BAL-DT Просмотр технического описания (PDF) - Agere -> LSI Corporation

Номер в каталогеКомпоненты Описаниепроизводитель
T-8207-BAL-DT CelXpres™ ATM Interconnect Agere
Agere -> LSI Corporation Agere
T-8207-BAL-DT Datasheet PDF : 158 Pages
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CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
Table of Contents (continued)
Figure
Page
Figure 1. Functional Block Diagram ......................................................................................................................... 9
Figure 2. Dual Bus Implementation ........................................................................................................................ 10
Figure 3. 272-Pin PBGA—Top View ...................................................................................................................... 19
Figure 4. Translation RAM Memory Map—8-Byte Records, for Up to 16 Ports ..................................................... 29
Figure 5. Translation RAM Memory Map—8-Byte Records, for Greater than 16 Ports...........................................30
Figure 6. Translation Record Types—8-Byte Records........................................................................................... 31
Figure 7. Translation RAM Flow Diagram .............................................................................................................. 35
Figure 8. Translation Record Types—Extended Mode .......................................................................................... 37
Figure 9. Translation RAM Memory Map—Extended Mode, for Up to 16 Ports..................................................... 38
Figure 10. Translation RAM Memory Map—Extended Mode, for Greater than 16 Ports ........................................39
Figure 11. Queue Priority Multiplexing ................................................................................................................... 46
Figure 12. TX UTOPIA Cell Handling ..................................................................................................................... 47
Figure 13. TX UTOPIA Bus Sharing....................................................................................................................... 49
Figure 14. Cell Bus Frame Format (Bit Positions for 16 User Mode) ..................................................................... 56
Figure 15. Cell Bus Frame Format (Bit Positions for 32 User Mode) ..................................................................... 57
Figure 16. Cell Bus Routing Headers ..................................................................................................................... 59
Figure 17. GTL+ External Circuitry ......................................................................................................................... 62
Figure 18. SDRAM Timing Parameters .................................................................................................................. 65
Figure 19. Crystal ................................................................................................................................................. 143
Figure 20. Negative Resistance Plot .................................................................................................................... 143
Figure 21. Nonmultiplexed Intel Mode Write Access Timing ................................................................................ 146
Figure 22. Nonmultiplexed Intel Mode Read Access Timing................................................................................ 146
Figure 23. Motorola Mode Write Access Timing................................................................................................... 148
Figure 24. Motorola Mode Read Access Timing .................................................................................................. 148
Figure 25. Multiplexed Intel Mode Write Access Timing....................................................................................... 150
Figure 26. Multiplexed Intel Mode Read Access Timing ...................................................................................... 150
Figure 27. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 153
Figure 28. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 153
Figure 29. Cell Bus Timing ................................................................................................................................... 155
Figure 30. SDRAM Interface Timing..................................................................................................................... 156
4
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