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T-8207-BAL-DT 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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T-8207-BAL-DT CelXpres™ ATM Interconnect Agere
Agere -> LSI Corporation Agere
T-8207-BAL-DT Datasheet PDF : 158 Pages
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Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
Table of Contents (continued)
Contents
Page
11 SDRAM Interface.............................................................................................................................................. 64
11.1 Memory Configuration............................................................................................................................. 64
11.2 Powerup Sequence................................................................................................................................. 64
11.3 SDRAM Interface Timing ........................................................................................................................ 65
11.4 Queuing .................................................................................................................................................. 66
11.5 SDRAM Refresh ..................................................................................................................................... 72
11.6 SDRAM Throughput................................................................................................................................ 73
12 Traffic Management.......................................................................................................................................... 74
12.1 Cell Loss Priority (CLP)........................................................................................................................... 74
12.2 Forward Explicit Congestion Notification (FECN) ................................................................................... 74
12.3 Partial Packet Discard (PPD) .................................................................................................................. 74
13 JTAG Test Access Port .................................................................................................................................... 75
13.1 Instruction Register ................................................................................................................................. 75
13.2 Boundary-Scan Register ......................................................................................................................... 76
14 Registers........................................................................................................................................................... 79
14.1 Register Types........................................................................................................................................ 79
14.2 Direct Memory Access Registers ............................................................................................................ 82
14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access
Registers 30h—37h ................................................................................................................... 86
14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access
Registers 30h—37h ................................................................................................................... 88
14.2.3 General-Purpose I/O Control Registers ..................................................................................... 90
14.2.4 Control Cells .............................................................................................................................. 91
14.2.5 Multicast Memories .................................................................................................................... 92
14.3 Extended Memory Registers................................................................................................................... 93
14.3.1 Main Registers ........................................................................................................................... 93
14.3.2 UTOPIA Registers ................................................................................................................... 106
14.3.2.1 TX UTOPIA Configuration ......................................................................................... 108
14.3.2.2 TX UTOPIA Monitoring .............................................................................................. 125
14.3.2.3 RX UTOPIA Monitoring.............................................................................................. 126
14.3.3 SDRAM Registers .................................................................................................................... 128
14.3.3.1 SDRAM Control Memory ........................................................................................... 135
14.3.4 Various Internal Memories ....................................................................................................... 137
14.3.4.1 Control Cell Memories ............................................................................................... 137
14.3.4.2 Multicast Number Memories ...................................................................................... 138
14.3.4.3 PPD State Memory ....................................................................................................140
14.3.5 External Memories ................................................................................................................... 141
14.3.5.1 Look-Up Translation Memory .................................................................................... 141
14.3.5.2 SDRAM Buffer Memory .............................................................................................141
15 Absolute Maximum Ratings ............................................................................................................................ 142
16 Recommended Operating Conditions............................................................................................................. 142
17 Handling Precautions...................................................................................................................................... 142
18 Electrical Requirements and Characteristics .................................................................................................. 143
18.1 Crystal Information................................................................................................................................ 143
18.2 dc Electrical Characteristics .................................................................................................................. 144
19 Timing Requirements...................................................................................................................................... 145
19.1 Microprocessor Interface Timing........................................................................................................... 146
19.2 UTOPIA Timing..................................................................................................................................... 152
19.3 External LUT Memory Timing ............................................................................................................... 153
19.4 Cell Bus Timing..................................................................................................................................... 155
19.5 SDRAM Interface Timing ...................................................................................................................... 156
20 Outline Diagram.............................................................................................................................................. 157
21 Ordering Information....................................................................................................................................... 158
Agere Systems Inc.
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