CXD3027R
Pin Description
Pin
No.
Symbol
I/O
1 A9
O 1, 0
2 A8
O 1, 0
3 A7
O 1, 0
4 DVSS
——
5 A6
O 1, 0
6 A5
O 1, 0
7 A4
O 1, 0
8 XWRE I
9 XRDE I
10 XEMP O 1, 0
11 XWIH O 1, 0
12 XQOK I
13 LRMU O 1, 0
14 SQSO O 1, 0
15 SQCK I
16 SCSY I
17 SCOR O 1, 0
18 VSS0
——
19 SBSO O 1, 0
20 EXCK I
21 XRST I
22 SYSM I
23 DATA I
24 XLAT
I
25 CLOK I
26 SENS
27 SCLK
28 XSOE
29 ATSK
30 R4M
31 VDD0
O 1, 0
I
I
I/O 1, 0
O
——
Description
4M-bit/16M-bit DRAM address bus 9.
4M-bit/16M-bit DRAM address bus 8.
4M-bit/16M-bit DRAM address bus 7.
DRAM interface GND
4M-bit/16M-bit DRAM address bus 6.
4M-bit/16M-bit DRAM address bus 5.
4M-bit/16M-bit DRAM address bus 4.
DRAM write enable signal.
DRAM readout enable signal.
DRAM readout prohibited signal.
DRAM write prohibited signal.
Subcode-Q OK input.
Lch, Rch "0" detection flag (AND output)
Subcode-Q 80-bit, PCM peak and level data output.
CD TEXT data output, DRAM data output.
SQSO readout clock input.
GRSCOR resynchronization input. High during track jump.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Digital GND.
Subcode P to W serial output.
SBSO readout clock input.
System reset. Reset when low.
Mute input. Muted when high.
Serial data input from CPU.
Latch input from CPU.
Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
SQSO or SENS readout clock is input by switching with the command.
SENS output to CPU.
SQSO data is output by switching with the command.
SENS serial data readout clock input.
CPU serial data output enable signal.
Anti-shock I/O.
Microcomputer clock output.
C4M is output by switching with the command.
Digital power supply.
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