CXD3027R
Command bit Sync protection window width
Application
WSEL = 1
±26 channel clock
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
∗ In normal-speed playback, channel clock = 4.3218MHz.
Command bit
Function
ASHS = 0
The command transfer rate from the auto sequencer to the DSSP block is set to normal speed.
ASHS = 1
The command transfer rate from the auto sequencer to the DSSP block is set to half speed.
∗ See "§4-8. CD-DSP Block Playback Speed" for settings.
Command bit
SOCT0 SOCT1
Processing
0
—
Subcode-Q is output from the SQSO pin.
1
0
Various signals are output from the SQSO pin. Input the readout clock to SQCK.
(See Timing Chart 2-4.)
1
1
The error rate is output from the SQSO pin. Input the readout clock to SQCK.
(See Timing Chart 2-6.)
∗ $8X command TXOUT = 0 and $A8X command SDTOOUT = 0 must be set.
—: don't care
Data 2
Data 3
Command
D3 D2 D1 D0 D3 D2 D1 D0
MODE
specification
VCO
SEL1
ASHS
SOCT0
VCO
SEL2
KSL3
KSL2
KSL1
KSL0
See above.
Command bit
VCOSEL1 = 0
VCOSEL1 = 1
Processing
Multiplier PLL VCO1 is set to normal speed.
Multiplier PLL VCO1 is set to approximately twice the normal speed.
Command bit
KSL3
KSL2
0
0
0
1
1
0
1
1
Processing
Output of multiplier PLL VCO1 selected by VCO CS0 is 1/1 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO CS0 is 1/2 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO CS0 is 1/4 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO CS0 is 1/8 frequency-divided.
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