T89C51RD2-SLRCM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
T89C51RD2-SLRCM Datasheet PDF : 104 Pages
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T89C51RD2
Bit
Bit
Number Mnemonic Description
0
S0
WDT Time-out select bit 0
S2 S1 S0Selected Time-out
0 0 0(214 - 1) machine cycles, 16.3 ms @ 12 MHz
0 0 1(215 - 1) machine cycles, 32.7 ms @ 12 MHz
0 1 0(216 - 1) machine cycles, 65.5 ms @ 12 MHz
0 1 1(217 - 1) machine cycles, 131 ms @ 12 MHz
1 0 0(218 - 1) machine cycles, 262 ms @ 12 MHz
1 0 1(219 - 1) machine cycles, 542 ms @ 12 MHz
1 1 0(220 - 1) machine cycles, 1.05 s @ 12 MHz
1 1 1(221 - 1) machine cycles, 2.09 s @ 12 MHz
Reset value XXXX X000
WDT During Power Down and
Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in
Power Down mode the user does not need to service the WDT. There are 2 methods of
exiting Power Down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power Down mode. When Power Down is exited with
hardware reset, servicing the WDT should occur as it normally should whenever the
T89C51RD2 is reset. Exiting Power Down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
T89C51RD2 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
If the WDT is activated, the power consumption in stand-by mode will be above the
specified value.
47
4243G–8051–05/03
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