T89C51RD2-RDTCM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
T89C51RD2-RDTCM Datasheet PDF : 104 Pages
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Warm Reset
Watchdog Reset
T89C51RD2
Table 26. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)
Oscillator
Start-Up Time
1 ms
VDD Rise Time
10 ms
100 ms
5 ms
820 nF
1.2 µF
12 µF
Note:
20 ms
2.7 µF
3.9 µF
12 µF
These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
As detailed in Section “Watchdog Timer”, the WDT generates a 96-clock period pulse
on the RST pin. In order to properly propagate this pulse to the rest of the application in
case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be
added as shown Figure 18.
Figure 18. Reset Circuitry for WDT Reset-out Usage
VDD
+
VDD
RST
P
VDD
1K
From WDT
Reset Source
To CPU Core
and Peripherals
RST
VSS
VSS
To Other
On-board
Circuitry
43
4243G–8051–05/03
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