T89C51RD2-SMSCM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
T89C51RD2-SMSCM Datasheet PDF : 104 Pages
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T89C51RD2
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 23. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
EA
EC
ET2
ES
3
2
1
0
ET1
EX1
ET0
EX0
Bit
Bit
Number Mnemonic Description
Enable All interrupt bit
Clear to disable all interrupts.
7
EA Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its own interrupt enable bit.
6
EC
PCA interrupt enable bit
Clear to disable . Set to enable.
Timer 2 overflow interrupt Enable bit
5
ET2 Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
Serial port Enable bit
4
ES Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
3
ET1 Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 Enable bit
2
EX1 Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
1
ET0 Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 Enable bit
0
EX0 Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
39
4243G–8051–05/03
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