Interrupt System
The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA glo-
bal interrupt. These interrupts are shown in Figure 16.
Figure 16. Interrupt Control System
INT0
IE0
TF0
INT1
IE1
TF1
PCA IT
RI
TI
IPH, IP
3
0
3
0
3
0
3
0
3
0
3
0
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
TF2
3
EXF2
0
Individual Enable
Global Disable
Low priority
interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register (See Table 23.). This register also contains a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority register (See Table 24.) and in the
Interrupt Priority High register (See Table 22). shows the bit values and priority levels
associated with each combination.
Table 22. Priority Level Bit Values
IPH.x
IP.x
0
0
0
1
1
0
1
1
Interrupt Level Priority
0 (Lowest)
1
2
3 (Highest)
38 T89C51RD2
4243G–8051–05/03