DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

T89C51RD2-SLRIM View Datasheet(PDF) - Atmel Corporation

Part Name
Description
Manufacturer
T89C51RD2-SLRIM
Atmel
Atmel Corporation Atmel
T89C51RD2-SLRIM Datasheet PDF : 104 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
Table 19. SADDR - Slave Address Register (A9h)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
Table 20. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
FE
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
SM1
Serial port Mode bit 1
SM0 SM1 Mode Description
Baud Rate
00
0
Shift Register FXTAL/12 (/6 in X2 mode)
01
1
8-bit UART Variable
10
2
9-bit UART FXTAL/64 or FXTAL/32 (/32 or 16 in X2 mode)
11
3
9-bit UART Variable
SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
TB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
TI
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of
the stop bit in the other modes.
Receive Interrupt flag
RI
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and
Figure 15. in the other modes.
Reset Value = 0000 0000b
Bit addressable
36 T89C51RD2
4243G805105/03
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]