T89C51RD2
Programmable Counter
Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accu-
racy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/ capture modules. Its clock input can be programmed to count
any one of the following signals:
• Oscillator frequency ÷ 12 (÷ 6 in X2 mode)
• Oscillator frequency ÷ 4 (÷ 2 in X2 mode)
• Timer 0 overflow
• External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
• rising and/or falling edge capture,
• software timer,
• high-speed output, or
• pulse width modulator.
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog
Timer", page 32).
When the compare/capture modules are programmed in the capture mode, software
timer, or high speed output mode, an interrupt can be generated when the module exe-
cutes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If one or several bits in the port are not used for the PCA,
they can still be used for standard I/O.
PCA component
External I/O Pin
16-bit Counter
16-bit Module 0
P1.2 / ECI
P1.3 / CEX0
16-bit Module 1
16-bit Module 2
P1.4 / CEX1
P1.5 / CEX2
16-bit Module 3
16-bit Module 4
P1.6 / CEX3
P1.7 / CEX4
The PCA timer is a common time base for all five modules (See Figure 7). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See
Table 10) and can be programmed to run at:
• 1/12 the oscillator frequency. (Or 1/6 in X2 Mode)
• 1/4 the oscillator frequency. (Or 1/2 in X2 Mode)
• The Timer 0 overflow
• The input on the ECI pin (P1.2)
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4243G–8051–05/03