T89C51RD2-SLRCM View Datasheet(PDF) - Atmel Corporation
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T89C51RD2-SLRCM Datasheet PDF : 104 Pages
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T89C51RD2
Table 7. Auxiliary Register (08EH)
AUXR
Address 08EH
-
-
M0
-
XRS1
XRS0
EXTRA
M
AO
Reset value
X
X
0
X
1
0
0
0
Symbol
-
Function
Not implemented, reserved for future use. (1)
AO
Disable/Enable ALE
AO
Operating Mode
0
ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used)
1
ALE is active only during a MOVX or MOVC instruction
EXTRAM Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR
EXTRAM Operating Mode
0
Internal XRAM access using MOVX @ Ri/ @ DPTR
1
External data memory access
XRS0
XRS1
XRAM size: Accessible size of the XRAM
XRS1:0 XRAM size
00
256 bytes
01
512 bytes
10
768 bytes (default)
11
1024 bytes
M0
Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the
value of M0
M0
Pulse length in clock period
0
6
1
30
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
17
4243G–8051–05/03
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