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T89C51RD2-SLRIM View Datasheet(PDF) - Atmel Corporation

Part Name
Description
Manufacturer
T89C51RD2-SLRIM
Atmel
Atmel Corporation Atmel
T89C51RD2-SLRIM Datasheet PDF : 104 Pages
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T89C51RD2
Figure 2. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
The X2 bit in the CKCON register (Table 4) allows to switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (Table 4)
allow to switch from standard peripheral speed (12 clock periods per peripheral clock
cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits
are active only in X2 mode.
More information about the X2 mode can be found in the application note ANM072 "How
to take advantage of the X2 features in TS80C51 microcontroller".
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
WdX2
PcaX2
SiX2
T2X2
T1X2
T0X2
X2
Bit
Bit
Number Mnemonic Description
7
-
Reserved
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
6
WdX2 Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect)
5
PcaX2 Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect)
4
SiX2 Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
3
T2X2 Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
11
4243G805105/03
 

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