T89C51RD2-SLSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
T89C51RD2-SLSIM Datasheet PDF : 104 Pages
| |||
Enhanced Features
X2 Feature and Clock
Generation
Description
In comparison to the original 80C52, the T89C51RD2 implements some new features,
which are:
• The X2 option
• The Dual Data Pointer
• The extended RAM
• The Programmable Counter Array (PCA)
• The Watchdog
• The 4 level interrupt priority system
• The power-off flag
• The ONCE mode
• The ALE disabling
• Some enhanced features are also located in the UART and the Timer 2
The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called
”X2” provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
XTAL1
FXTAL
XTAL1:2
2
0
1
FOSC
State Machine: 6 clock cycles.
CPU control.
X2
CKCON reg
10 T89C51RD2
4243G–8051–05/03
|
|
Share Link: 