STE2007DIE2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STE2007DIE2

96 x 68 Single-chip LCD controller/driver

STMicroelectronics 

Interface

STE2007

4.3.4

Driver TxData mode (Read mode)

If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If

the D/C bit during the last write access, is set to a logic 0, the byte read is the status byte.

Figure 18. Communication protocol

WRITE MODE

STE2007 ACK

COMMUNICATION

START

I2C START 0 1 1 1 1 SA1 SA2 0 A

COND

R/W

SLAVE ADDRESS

Co D/C

STE2007 ACK

STE2007 ACK

SINGLE COMMAND

SEQUENCE

1 0 0 0 0 0 0 0 A COMMAND Byte A

Control Byte

Command Byte

Co D/C

STE2007 ACK

STE2007 ACK

STE2007 ACK

MULTIPLE COMMAND 0 0 0 0 0 0 0 0 A COMMAND Byte A

SEQUENCE

COMMAND Byte A

Control Byte

First Command Byte

Last Command Byte

Co D/C

STE2007 ACK

STE2007 ACK

SINGLE DATA

SEQUENCE

1 1 0 0 0 0 0 0 A DATA Byte A

Control Byte

Data Byte

Co D/C

STE2007 ACK

STE2007 ACK

STE2007 ACK

MULTIPLE DATA

SEQUENCE

0 1 0 0 0 0 0 0 A DATA Byte A

DATA Byte A

Control Byte

First Data Byte

Last Data Byte

COMMUNICATION

STOP

I2C STOP

COND

READ MODE

STE2007 ACK

MASTER ACK

STATUS BYTE READ

SEQUENCE

I2C START

COND

0

1

1

1

1 SA1 SA2 0 A

STATUS Byte

A

I2C START

COND

R/W

SLAVE ADDRESS

LR0008d

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