STE2007DIE2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STE2007DIE2 Datasheet PDF : 62 Pages
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Interface
STE2007
Figure 13. 4-lines SPI Data transfer pause
Pause
!CS
D/!C
SCL
SDA
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0191
4.2.2
Driver TxData Mode (read mode)
Throughout SDA line is possible to read some registers value (ID Numbers, Status byte,
temperature).
SDA (output Driver) is in High impedance in steady state and during data write.
Figure 14. 4-lines SPI 8-Bit read cycle
Read Command
!CS
D!C
SCL
DATA
Next Command
SDA
(Input)
SDA
(Output)
D7 D6 D5 D4 D3 D2 D1 D0
High Z
High Z
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
MCU Data Tx Start
LCD Driver Data Tx Start
MCU Data Tx Start
LR0255
4.3
I2C Bus
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
– Data transfer may be initiated only when the bus is not busy.
– During data transfer, the data line must remain stable whenever the clock line is
high. Changes in the data line while the clock line is high will be interpreted as a
Start or Stop Data Transfer condition (see below).
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
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