Register description
STA333BWQS
6.4.7
6.4.8
Zero-detect mute enable
Table 34. Zero-detect mute enable
Bit R/W RST
Name
6
R/W
1
ZDE
Description
Setting of 1 enables the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at
the data for each processing channel at the output of the crossover (bass management)
filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then
that individual channel is muted if this function is enabled.
MiamiMode enable
Table 35. MiamiMode enable
Bit R/W RST
Name
7
R/W
0
MME
Description
0: sub mix into left/right disabled
1: sub mix into left/right enabled
6.5
6.5.1
6.5.2
Configuration register E (0x04)
D7
SVE
1
D6
ZCE
1
D5
DCCV
0
D4
PWMS
0
D3
AME
0
D2
NSBW
0
D1
MPC
1
Max power correction variable
Table 36. Max power correction variable
Bit R/W RST
Name
Description
0
R/W
0
MPCV
0: use standard MPC coefficient
1: use MPCC bits for MPC coefficient
D0
MPCV
0
Max power correction
Table 37. Max power correction
Bit R/W RST
Name
1
R/W
1
MPC
Description
Setting of 1 enables Power Bridge correction for
THD reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA333BWQS power
device at high power. This mode should lower the THD+N of a full DDX system at maximum
power output and slightly below. If enabled, MPC is operational in all output modes except
tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4,
the line-out channels.
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