STA323W
7.6 CONFIGURATION REGISTER E (ADDRESS 04H)
D7
D6
D5
D4
D3
SVE
ZCE
RES
PWMS
AME
0
0
0
0
0
D2
RES
0
D1
MPC
0
D0
MPCV
0
7.6.1 Max Power Correction Variable
BIT
R/W
RST
NAME
DESCRIPTION
0
R/W
0
MPCV
Max Power Correction Variable:
0 – Use Standard MPC Coefficient
1 – Use MPCC bits for MPC Coefficient
By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the
MPCC registers (address 0x27-0x28) it becomes possible to adjust the THD at maximum unclipped power
to a lower value for a particular application.
7.6.2 Max Power Correction
BIT
R/W
RST
NAME
DESCRIPTION
7
R/W
1
MPC
Max Power Correction:
0 – MPC Disabled
1 – MPC Enabled
Setting the MPC bit corrects the DDX-2060/2100/2160 power device at high power. This mode will lower
the THD+N of a full DDX-2060 DDX® system at maximum power output and slightly below.
7.6.3 AM Mode Enable
BIT
R/W
RST
NAME
DESCRIPTION
3
R/W
0
AME
AM Mode Enable:
0 – Normal DDX® operation.
1 – AM reduction mode DDX® operation.
The STA323W features a DDX® processing mode that minimizes the amount of noise generated in the
frequency range of AM radio. This mode is intended for use when DDX® is operating in a device with an
active AM tuner. The SNR of the DDX® processing is reduced to ~83dB in this mode, which is still greater
than the SNR of AM radio.
7.6.4 PWM Speed Mode
BIT R/W RST
4
R/W
0
NAME
PWMS
DESCRIPTION
PWM Speed Selection: Normal or Odd
Table 14. PWM Output Speed Selections
PWMS (1...0)
0
1
PWM Output Speed
Normal Speed (384kHz) All Channels
Odd Speed (341.3kHz) All Channels
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