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STA323WQS View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
STA323WQS Datasheet PDF : 78 Pages
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STA323WQS
Description
1.1
Block diagram and configurations
Figure 1. Block diagram
SDA
SCL
I2C
System control
LRCKI
BICKI
SDI_12
Serial data
input, channel
mapping and
resampling
Audio EQ, mix,
crossover,
volume, limiter
processing
DDX
processing
System timing
Power down
CLK
TWARN
FAULT
Power down
Quad
half-bridge
power stage
OUT1A
OUT1B
OUT2A
OUT2B
EAPD
Figure 2. Channel signal flow diagram through the digital core
I2S
input Channel
mapping
Re-sampling
ED
processing
Mix
Crossover Volume
filter
limiter
4x
Interpol
DDX
DDX
output
1.2
EQ processing
Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ
processing block. In these blocks, up to four user-defined Biquads can be applied to each of
the two channels.
Pre-scaling, DC-blocking high-pass, de-emphasis, bass, and tone control filters can also be
implemented by means of configuration parameter settings.
The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB
bit to '1'. The CxEQBP bits can also be used to bypass the EQ functionality on a per channel
basis. Figure 3 shows the internal signal flow through the EQ block.
Figure 3. Channel signal flow diagram through the EQ block
Re-sampled
input
pre-scale
High pass
filter
BQ#1
BQ#2
BQ#3
BQ#4
De-
emphasis
Bass
filter
To
Treble
mix
filter
If HPB= 0
4 biquads
User defined if AMEQ = 00
Preset EQ if AMEQ = 01
Auto loudness if AMEQ = 10
If CxTCB = 0
If DEMP = 1 BTC: bass boost/cut
TTC: treble boost/cut
If DSPB = 0 and CxEQB = 0
11/78
 

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