ST92T195C8B1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92T195C8B1

48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER

STMicroelectronics 

ST92195C/D

48-96 Kbyte ROM HCMOS MCU WITH

ON-SCREEN DISPLAY AND TELETEXT DATA SLICER

s Register File based 8/16 bit Core Architecture

with RUN, WFI, SLOW and HALT modes

s 0°C to +70°C operating temperature range

s Up to 24 MHz. operation @ 5V±10%

s Min. instruction cycle time: 165ns at 24 MHz.

s 48, 56, 64, 84 or 96 Kbytes ROM

s 256 bytes RAM of Register file (accumulators or

index registers)

s 256 to 512 bytes of on-chip static RAM

s 2 or 8 Kbytes of TDSRAM (Teletext and Display

Storage RAM)

s 28 fully programmable I/O pins

s Serial Peripheral Interface

s Flexible Clock controller for OSD, Data Slicer

and Core clocks running from a single low

frequency external crystal.

s Enhanced display controller with 26 rows of

40/80 characters

– 2 sets of 512 characters

– Serial and Parallel attributes

– 10x10 dot matrix, definable by user

– 4/3 and 16/9 supported in 50/60Hz and 100/

120 Hz mode

– Rounding, fringe, double width, double height,

scrolling, cursor, full background color, half-

intensity color, translucency and half-tone

modes

s Teletext unit, including Data Slicer, Acquisition

Unit and up to 8 Kbytes RAM for data storage

s VPS and Wide Screen Signalling slicer

s Integrated Sync Extractor and Sync Controller

s 14-bit Voltage Synthesis for tuning reference

voltage

s Up to 6 external interrupts plus one Non-

Maskable Interrupt

s 8 x 8-bit programmable PWM outputs with 5V

open-drain or push-pull capability

s 16-bit watchdog timer with 8-bit prescaler

s 1 or 2 16-bit standard timer(s) with 8-bit

prescaler

PSDIP56

TQFP64

See end of Datasheet for ordering information

s I²C Master/Slave (on some devices)

s 4-channel A/D converter; 5-bit guaranteed

s Rich instruction set and 14 addressing modes

s Versatile development tools, including

Assembler, Linker, C-compiler, Archiver,

Source Level Debugger and hardware

emulators with Real-Time Operating System

available from third parties

s Pin-compatible EPROM and OTP devices

available

Device Summary

Device ROM RAM TDSRAM I²C Timer

ST92195C3

256

2K

ST92195C4 48K

6K

ST92195C5

ST92195C6 56K

No 1

512

ST92195C7 64K

8K

ST92195C8 84K

ST92195C9 96K

ST92195D5 48K

ST92195D6 56K 512

8K Yes 2

ST92195D7 64K

October 2003

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