SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SI. AVD interrupt causes the
device to exit from Wait mode.
The CRSR register is frozen.
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the AVDIE bit is set and the interrupt mask in the
CC register is reset (RIM instruction).
Interrupt Event
AVD event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
AVDF AVDIE Yes
Exit
from
Halt
No
ST72324Jx ST72324Kx
29/164
1