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ST72324BL View Datasheet(PDF) - STMicroelectronics

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Description
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ST72324BL Datasheet PDF : 151 Pages
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ST72F324L, ST72324BL
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 10.
For more details, refer to dedicated parametric
section.
Main features
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
Section 6.1 on page 22.
Caution: The PLL must not be used with the inter-
nal RC oscillator.
Figure 10. Clock, Reset and Supply Block Diagram
OSC2
OSC1
RESET
MULTI-
fOSC
OSCILLATOR
(MO)
PLL Block
PLL x 2
/2
0
fOSC2
1
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
fCPU
PLL OPTION BIT
RESET SEQUENCE
MANAGER
(RSM)
WATCHDOG
TIMER (WDG)
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