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ST72324 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST72324 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST72324 Datasheet PDF : 163 Pages
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ST72324
INTERRUPTS (Cont’d)
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
7
0
IS11 IS10 IPB IS21 IS20 IPA 0
0
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
IS11 IS10
00
01
10
11
External Interrupt Sensitivity
IPB bit =0
IPB bit =1
Falling edge &
low level
Rising edge
& high level
Rising edge only Falling edge only
Falling edge only Rising edge only
Rising and falling edge
- ei3 (port B4)
IS11 IS10
00
01
10
11
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
- ei0 (port A3..0)
IS21 IS20
00
01
10
11
External Interrupt Sensitivity
IPA bit =0
IPA bit =1
Falling edge &
low level
Rising edge
& high level
Rising edge only Falling edge only
Falling edge only Rising edge only
Rising and falling edge
- ei1 (port F2..0)
IS21 IS20
00
01
10
11
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.
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