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ST72324 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST72324 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST72324 Datasheet PDF : 163 Pages
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ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a VIT-(AVD) and
VIT+(AVD) reference value and the VDD main sup-
ply. The VIT- reference value for falling voltage is
lower than the VIT+ reference value for rising volt-
age in order to avoid parasitic detection (hystere-
sis).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte (see Sec-
tion 14.1 on page 150).
6.4.2.1 Monitoring the VDD Main Supply
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 16.
The interrupt on the rising edge is used to inform
the application that the VDD warning state is over.
If the voltage rise time trv is less than 256 or 4096
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles then:
– If the AVD interrupt is enabled before the
VIT+(AVD) threshold is reached, then 2 AVD inter-
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
– If the AVD interrupt is enabled after the VIT+(AVD)
threshold is reached then only one AVD interrupt
will occur.
Figure 16. Using the AVD to Monitor VDD
VDD
VIT+(AVD)
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
trv VOLTAGE RISE TIME
AVDF bit
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
1
RESET VALUE
INTERRUPT PROCESS
1
0
INTERRUPT PROCESS
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