ST24E64 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST24E64

SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM

STMicroelectronics 

ST24E64, ST25E64

Figure 2A. DIP Pin Connections

ST24E64

ST25E64

E0 1

E1 2

8 VCC

7 WC

E2 3

6 SCL

VSS 4

5 SDA

AI01205B

Figure 2B. SO Pin Connections

E0

E1

E2

VSS

ST24E64

ST25E64

1

8

2

7

3

6

4

5

AI01206C

VCC

WC

SCL

SDA

Table 2. Absolute Maximum Ratings (1)

Symbol

Parameter

Value

Unit

TA

TSTG

TLEAD

Ambient Operating Temperature

Storage Temperature

Lead Temperature, Soldering

(SO8)

(PSDIP8)

–40 to 125

°C

–65 to 150

°C

40 sec

10 sec

215

260

°C

VIO

Input or Output Voltages

–0.6 to 6.5

V

VCC

Supply Voltage

–0.3 to 6.5

V

VESD

Electrostatic Discharge Voltage (Human Body model) (2)

Electrostatic Discharge Voltage (Machine model) (3)

4000

V

500

V

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and

other relevant quality documents.

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d)

Each memory is compatible with the I2C extended

addressing standard, two wire serial interface

which uses a bi-directional data bus and serial

clock. The ST24/25E64carry a built-in 4 bit, unique

device identification code (1010) corresponding to

the I2C bus definition. The ST24/25E64 behave as

slave devices in the I2C protocol with all memory

operations synchronized by the serial clock. Read

and write operations are initiated by a START

conditiongenerated by the bus master. The START

condition is followed by a stream of 4 bits (identifi-

cation code 1010), 3 bit Chip Enable input to form

a 7 bit Device Select, plus one read/write bit and

terminated by an acknowledge bit.

2/16

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